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David Schneider committed 50e839c

Start implementing float load and store instructions

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  • Parent commits a907131
  • Branches arm-backend-2

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Files changed (3)

File pypy/jit/backend/arm/instruction_builder.py

         self.write32(instr)
 
     return f
+def define_float_load_store_func(name, table):
+    n = (0x3 << 26
+        | (table['opcode'] & 0x1F) << 20
+        | 0x5 << 0x9
+        | 0x1 << 0x8)
+
+    def f(self, dd, rn, imm=0, cond=cond.AL):
+        u, imm = self._encode_imm(imm)
+        instr = ( n
+                | (cond & 0xF) << 28
+                | (u & 0x1) << 23
+                | (rn & 0xF) << 16
+                | (dd & 0xF) << 12
+                | (imm & 0xFF))
+        self.write32(instr)
+    return f
 
 def define_float64_data_proc_instructions_func(name, table):
     n = (0xE << 24

File pypy/jit/backend/arm/instructions.py

     'SMLAL': {'op':0xE, 'long': True},
 }
 
+float_load_store = {
+    'VSTR':    {'opcode': 0x10},
+    'VLDR':    {'opcode': 0x11},
+}
+
+
 # based on encoding from A7.5	VFP data-processing instructions
 # opc2 is one of the parameters and therefore ignored here
 float64_data_proc_instructions = {

File pypy/jit/backend/arm/test/test_instr_codebuilder.py

     def setup_method(self, ffuu_method):
         self.cb = CodeBuilder()
 
+def gen_test_float_load_store_func(name, table):
+    tests = []
+    for c,v in [('EQ', conditions.EQ), ('LE', conditions.LE), ('AL', conditions.AL)]:
+        for reg in range(16):
+            if reg == 14:
+                tests.append(lambda self: py.test.skip('r14(lr) gives strange results'))
+                continue
+
+            for creg in range(16):
+                asm = 'd%d, [r%d]' % (creg, reg)
+                tests.append((asm, (creg, reg)))
+                #asm = 'd%d, [r%d, #4]' % (creg, reg)
+                #tests.append((asm, (creg, reg, 4)))
+    return tests
+
 def gen_test_float64_data_proc_instructions_func(name, table):
     tests = []
     for c,v in [('EQ', conditions.EQ), ('LE', conditions.LE), ('AL', conditions.AL)]: