Commits

Alex Gaynor  committed d15aec4 Merge

Merged upstream.

  • Participants
  • Parent commits eabb1fc, e896633

Comments (0)

Files changed (3)

File pypy/jit/backend/x86/assembler.py

             cls = self.cpu.gc_ll_descr.has_write_barrier_class()
             assert cls is not None and isinstance(descr, cls)
         loc_base = arglocs[0]
-        if isinstance(loc_base, RegLoc):
-            self.mc.TEST8_mi((loc_base.value, descr.jit_wb_if_flag_byteofs),
-                             descr.jit_wb_if_flag_singlebyte)
-        else:
-            assert isinstance(loc_base, ImmedLoc)
-            self.mc.TEST8_ji(loc_base.value + descr.jit_wb_if_flag_byteofs,
-                             descr.jit_wb_if_flag_singlebyte)
+        self.mc.TEST8(addr_add_const(loc_base, descr.jit_wb_if_flag_byteofs),
+                      imm(descr.jit_wb_if_flag_singlebyte))
         self.mc.J_il8(rx86.Conditions['Z'], 0) # patched later
         jz_location = self.mc.get_relative_pos()
         # the following is supposed to be the slow path, so whenever possible

File pypy/jit/backend/x86/regloc.py

     SHR = _binaryop('SHR')
     SAR = _binaryop('SAR')
     TEST = _binaryop('TEST')
+    TEST8 = _binaryop('TEST8')
 
     ADD = _binaryop('ADD')
     SUB = _binaryop('SUB')

File pypy/jit/backend/x86/rx86.py

     # The 64-bit version of this, CQO, is defined in X86_64_CodeBuilder
     CDQ = insn(rex_nw, '\x99')
 
-    TEST8_mi = insn(rex_w, '\xF6', orbyte(0<<3), mem_reg_plus_const(1), immediate(2, 'b'))
-    TEST8_ji = insn(rex_w, '\xF6', orbyte(0<<3), '\x05', immediate(1), immediate(2, 'b'))
+    TEST8_mi = insn(rex_nw, '\xF6', orbyte(0<<3), mem_reg_plus_const(1), immediate(2, 'b'))
+    TEST8_ji = insn(rex_nw, '\xF6', orbyte(0<<3), '\x05', immediate(1), immediate(2, 'b'))
     TEST_rr = insn(rex_w, '\x85', register(2,8), register(1), '\xC0')
 
     # x87 instructions