Add leanbit

[William Roberts]

Use free bit in encoding to drop 2nd word immediate. By setting the bit to a 1, lean mode is activated and instructions are only one word, and imply a second (immediate) word of 0. These leaves the first word instruction format the same and only needs to modify the increment in fetch.

[William "Amos" Confer]

Currently, the instruction bus is two words wide, and the low and high instruction words are acquired at once, in the same pipeline stage and cycle.

The lean bit must not be implemented as to require the low word's lean bit be evaluated after a first transfer, thus possibly requiring a second transfer. Realistically, that would require a second fetch stage in the pipeline and changes the core model.

Similarly, the PC queue is updated prior to fetch completion. Could we increment the PC by 1 or 2 correctly during the first fetch without stretching reality?

[William Roberts]

I would implement this as:

0 fetch 2 words A and B 1 fetch keeps B Decode has A 2 fetch fetches C and D and pushes B

So every other clock gets a fetch and it just pushes one word at a time

[William "Amos" Confer]

so fetch ends up with old B and a new A and B each cycle? How does it update the NPC and PC without messing anything up when a fetched but yet unknown sized delay slot instruction is immediately followed by the first instruction of a new branch target? Branch prediction would have to be delayed by an extra cycle too then...

So basically that potential solution would have to have a Fetch, Dec/Fetch2, Decode2 (for RLOADs and branches when immediate unknown at beginning of Dec/Fetch2), Exec, and Write Back stages. Extending the pipeline to include a decoding decode stage.

I'm not certain there isn't a viable solution piece, here, but I'd love to keep the MiniAT away from a decoding decode stage like we've had all along. It's one of its most unique characteristics. I'll think about it some more.