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MyHldXilinxUnisimLib lets you use Xilinx Unisim components within a MyHDL project

MyHldXilinxUnisimLib is intended to be used in a VHDL workflow.

To generate the library yourself, you have to :
- Copy the file unisim_VCOMP.vhd from your Xilinx installation to the ./src directory
- Run the ./src/MyHldXilinxUnisimLibGenerator.py script (using Python 3)

The generated library is located in ./output directory.

Simple examples are located in ./example directory.

Some components, like PCIE_2_0 can't be managed because they have either too 
many ports or too many generics. However, these components are too complex
to be used manually. So, this is not an issue.

TODO :
- Add simulation models