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Alex Gaynor committed bea486d Merge

merged upstream

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Files changed (5)

pypy/jit/backend/arm/codebuilder.py

         self._VCVT(target, source, cond, 0, 1)
 
     def _VCVT(self, target, source, cond, opc2, sz):
-        D = 0x0
+        D = 0
         M = 0
         op = 1
         instr = (cond << 28
                 | (source & 0xF))
         self.write32(instr)
 
+    def _VCVT_single_double(self, target, source, cond, sz):
+        # double_to_single = (sz == '1');
+        D = 0
+        M = 0
+        instr = (cond << 28
+                | 0xEB7 << 16
+                | 0xAC << 4
+                | D << 22
+                | (target & 0xF) << 12
+                | sz << 8
+                | M << 5
+                | (source & 0xF))
+        self.write32(instr)
+
+    def VCVT_f64_f32(self, target, source, cond=cond.AL):
+        self._VCVT_single_double(target, source, cond, 1)
+
+    def VCVT_f32_f64(self, target, source, cond=cond.AL):
+        self._VCVT_single_double(target, source, cond, 0)
+
     def POP(self, regs, cond=cond.AL):
         instr = self._encode_reg_list(cond << 28 | 0x8BD << 16, regs)
         self.write32(instr)

pypy/jit/backend/arm/opassembler.py

         self.mc.MOV_ri(r.ip.value, 0)
         self.mc.VMOV_cr(res.value, tmp.value, r.ip.value)
         return fcond
+
+    def emit_op_cast_float_to_singlefloat(self, op, arglocs, regalloc, fcond):
+        arg, res = arglocs
+        assert arg.is_vfp_reg()
+        assert res.is_reg()
+        self.mc.VCVT_f64_f32(r.vfp_ip.value, arg.value)
+        self.mc.VMOV_rc(res.value, r.ip.value, r.vfp_ip.value)
+	return fcond
+    
+    def emit_op_cast_singlefloat_to_float(self, op, arglocs, regalloc, fcond):
+        arg, res = arglocs
+        assert res.is_vfp_reg()
+        assert arg.is_reg()
+        self.mc.MOV_ri(r.ip.value, 0)
+        self.mc.VMOV_cr(res.value, arg.value, r.ip.value)
+        self.mc.VCVT_f32_f64(res.value, res.value)
+        return fcond

pypy/jit/backend/arm/regalloc.py

         res = self.vfprm.force_allocate_reg(op.result)
         return [loc, res]
 
+    def prepare_op_cast_float_to_singlefloat(self, op, fcond):
+        loc1 = self._ensure_value_is_boxed(op.getarg(0))
+        res = self.force_allocate_reg(op.result)
+        return [loc1, res]
+    
+    def prepare_op_cast_singlefloat_to_float(self, op, fcond):
+        loc1 = self._ensure_value_is_boxed(op.getarg(0))
+        res = self.force_allocate_reg(op.result)
+        return [loc1, res]
+
 
 def add_none_argument(fn):
     return lambda self, op, fcond: fn(self, op, None, fcond)

pypy/jit/backend/arm/runner.py

     supports_floats = True
     supports_longlong = False # XXX requires an implementation of
                               # read_timestamp that works in user mode
+    supports_singlefloats = True
     
     use_hf_abi = False        # use hard float abi flag
 

pypy/jit/backend/arm/test/test_float.py

+
+import py
+from pypy.jit.backend.arm.test.support import JitARMMixin
+from pypy.jit.metainterp.test.test_float import FloatTests
+
+class TestFloat(JitARMMixin, FloatTests):
+    # for the individual tests see
+    # ====> ../../../metainterp/test/test_float.py
+    pass
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