In the comments of MyHDL designs, the corresponding verilog/vhdl-file-names are shown, which can be downloaded from the website.
Please see the Verilog/VHDL tutorials for better understanding of the resultant designs.
Following is the list of MyHDL-keywords which are used in this tutorial. Also relationship between these keywords with Verilog/VHDL are shown in below table,
Keywords Verilog VHDL Signal reg, wire signal bool reg, wire std_logic intbv(0)[N:0] reg, wire unsigned enum reg, wire type if,else if,else or case if,else or case tuple of int case statement for ROM case statement for ROM list of bool reg array of std_logic list of intbv reg array of unsigned def module entity @always @always process @always_comb @always* process(all) @always_seq @always with initial values of reg/wire process with initial values of signals ResetSignal used with @always_seq to define reset signal posedge/negedge posedge/negedge rising_edge/falling_edge