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Armin Rigo  committed 469c780

Starting work on the x86 backend

  • Participants
  • Parent commits 99d2cae
  • Branches stm-jit

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Files changed (2)

File pypy/jit/backend/x86/regalloc.py

             if self.can_merge_with_next_guard(op, i, operations):
                 oplist_with_guard[op.getopnum()](self, op, operations[i + 1])
                 i += 1
-            elif not we_are_translated() and op.getopnum() == -124:
-                self._consider_force_spill(op)
+            elif not we_are_translated() and op.getopnum() < 0:
+                if op.getopnum() == -124:
+                    self._consider_force_spill(op)
+                elif op.getopnum() == -123:
+                    self._consider_escape(op)
+                else:
+                    assert 0, op
             else:
                 oplist[op.getopnum()](self, op)
             if op.result is not None:
         # This operation is used only for testing
         self.force_spill_var(op.getarg(0))
 
+    def _consider_escape(self, op):
+        # This operation is used only for testing:
+        # it checks that op.getarg(0) is currently not in a reg
+        loc = self.loc(op.getarg(0))
+        assert not isinstance(loc, RegLoc)
+
     def get_mark_gc_roots(self, gcrootmap, use_copy_area=False):
         shape = gcrootmap.get_basic_shape()
         for v, val in self.fm.bindings.items():
     def consider_keepalive(self, op):
         pass
 
+    def consider_stm_read_before(self, op):
+        self.xrm.before_call(save_all_regs=True)
+        self.rm.before_call(save_all_regs=True)
+
     def not_implemented_op(self, op):
         not_implemented("not implemented operation: %s" % op.getopname())
 

File pypy/jit/backend/x86/test/test_stm_integration.py

+
+""" Tests for register allocation for common constructs
+"""
+
+import py
+from pypy.jit.backend.x86.test.test_regalloc import BaseTestRegalloc
+
+
+class TestStm(BaseTestRegalloc):
+
+    def test_stm_read_before_spills_all(self):
+        # for now, stm_read_before() first spills all registers
+        ops = '''
+        [i1, i2]
+        i3 = int_add(i1, i2)
+        stm_read_before()
+        escape(i3)         # assert i3 was spilled
+        finish(i3)
+        '''
+        self.interpret(ops, [40, 2])
+        res = self.cpu.get_latest_value_int(0)
+        assert res == 42