Snippets
Created by
ScorpionIlluminati
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; Scorpion Illuminati
;==============================================================
; SEGA Genesis SegaDev 2014
;==============================================================
__start:
; ******************************************************************
; Sega Megadrive ROM header
; ******************************************************************
dc.l 0x00FFE000 ; Initial stack pointer value
dc.l EntryPoint ; Start of program
dc.l BusErrorException ; Bus error
dc.l AddressErrorException ; Address error
dc.l IllegalInstructionException ; Illegal instruction
dc.l ZeroDivideException ; Division by zero
dc.l CHKInstructionException ; CHK exception
dc.l TRAPVInstructionException ; TRAPV exception
dc.l PrivilegeViolationException ; Privilege violation
dc.l NullInterrupt ; TRACE exception
dc.l LineAEmulator ; Line-A emulator
dc.l LineFEmulator ; Line-F emulator
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Spurious exception
dc.l NullInterrupt ; IRQ level 1
dc.l NullInterrupt ; IRQ level 2
dc.l NullInterrupt ; IRQ level 3
dc.l HBlankInterrupt ; IRQ level 4 (horizontal retrace interrupt)
dc.l NullInterrupt ; IRQ level 5
dc.l VBlankInterrupt ; IRQ level 6 (vertical retrace interrupt)
dc.l NullInterrupt ; IRQ level 7
dc.l NullInterrupt ; TRAP #00 exception
dc.l NullInterrupt ; TRAP #01 exception
dc.l NullInterrupt ; TRAP #02 exception
dc.l NullInterrupt ; TRAP #03 exception
dc.l NullInterrupt ; TRAP #04 exception
dc.l NullInterrupt ; TRAP #05 exception
dc.l NullInterrupt ; TRAP #06 exception
dc.l NullInterrupt ; TRAP #07 exception
dc.l NullInterrupt ; TRAP #08 exception
dc.l NullInterrupt ; TRAP #09 exception
dc.l NullInterrupt ; TRAP #10 exception
dc.l NullInterrupt ; TRAP #11 exception
dc.l NullInterrupt ; TRAP #12 exception
dc.l NullInterrupt ; TRAP #13 exception
dc.l NullInterrupt ; TRAP #14 exception
dc.l NullInterrupt ; TRAP #15 exception
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
dc.l NullInterrupt ; Unused (reserved)
;*******************************************************************
; Genesis
;*******************************************************************
dc.b "SEGA MEGA DRIVE " ; Console name
dc.b "(C)SEGA 1992.SEP" ; Copyrght holder and release date
dc.b "Scorpion Illuminati " ; Domestic name
dc.b "Scorpion Illuminati " ; International name
dc.b "GM XXXXXXXX-00" ; Version number
dc.b " " ; Checksum
dc.b "J6 " ; I/O support
dc.l __start ; Start address of ROM
dc.l __end-1 ; End address of ROM
dc.l 0x00FF0000 ; Start address of RAM
dc.l 0x00FFFFFF ; End address of RAM
dc.b " " ; SRAM enabled
dc.b " " ; Unused
dc.b " " ; Start address of SRAM
dc.b " " ; End address of SRAM
dc.b " " ; Unused
dc.b " " ; Unused
dc.b " " ; Notes (unused)
dc.b "F " ; Country codes
;*******************************************************************
; Mega-CD
;*******************************************************************
dc.b "SEGADISCSYSTEM "
dc.b "CDBOOTLOADR",0
dc.w 0x0100
dc.w 0x0001
dc.b "SEGACD BOOT",0
dc.w 0x0001
dc.w 0x0000
dc.l 0x00000800 ; Main CPU ROM offset
dc.l 0x00000800 ; Main CPU ROM size
dc.l 0x00000000 ; Main CPU ROM start offset
dc.l 0x00000000 ; Main CPU work RAM size
dc.l 0x00001000 ; Sub CPU ROM offset
dc.l 0x00007000 ; Sub CPU ROM size
dc.l 0x00000000 ; Sub CPU ROM start offset
dc.l 0x00000000 ; Sub CPU ROM work RAM size
dc.b "09102014" ; Date
|
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 | ;==============================================================
; BIG EVIL CORPORATION .co.uk
;==============================================================
; SEGA Genesis Framework (c) Matt Phillips 2014
;==============================================================
; interpts.asm - Interrupts and exceptions
;==============================================================
HBlankInterrupt:
addi.l #0x1, hblank_counter ; Increment hinterrupt counter
rte
VBlankInterrupt:
; Backup registers
movem.l d0-a7,-(sp)
; Cache Joypad inputs
jsr ReadPadA
jsr ReadPadB
addi.l #0x1, vblank_counter ; Increment vinterrupt counter
TRAP #0 ; Sync with debugger - NOT FOR RELEASE
; Restore registers
movem.l (sp)+,d0-a7
rte
Exception:
TRAP #0 ; Sync with debugger - NOT FOR RELEASE
stop #$2700 ; Halt CPU
TRAP #0 ; Sync with debugger - NOT FOR RELEASE
jmp Exception
rte
BusErrorException:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea BusErrorString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
AddressErrorException:
move.w 8(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea AddressErrorString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
IllegalInstructionException:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea IllegalInstructionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
ZeroDivideException:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea ZeroDivideString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
CHKInstructionException:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea CHKInstructionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAPVInstructionException:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAPVInstructionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
PrivilegeViolationException:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea PrivilegeViolationString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRACEException:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRACEString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
LineAEmulator:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea LineAEmulatorString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
LineFEmulator:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea LineFEmulatorString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP00Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP00ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP01Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP01ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP02Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP02ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP03Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP03ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP04Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP04ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP05Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP05ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP06Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP06ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP07Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP07ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP08Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP08ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP09Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP09ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP10Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP10ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP11Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP11ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP12Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP12ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP13Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP13ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP14Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP14ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
TRAP15Exception:
move.w 2(sp), (backup_pc) ; save pc state
move.l a0, (register_backup_a0) ; save a0 register state
lea TRAP15ExceptionString, a0 ; load effective address for error code
move.l a0, (error_code) ; store error code in ram
jmp CrashHandler_Init ; jump to crash handler
stop #$2700 ; Halt CPU
rte
NullInterrupt:
rte
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