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Anonymous committed 00b4c90

[ARM SMP] Use event instructions for spinlocks

ARMv6K CPUs have SEV (send event) and WFE (wait for event) instructions
which allow the CPU clock to be suspended until another CPU issues a
SEV, rather than spinning on the lock wasting power. Make use of these
instructions.

Note that WFE does not wait if an event has been sent since the last WFE
cleared the event status, so although it may look racy, the instruction
implementation ensures that these are dealt with.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Comments (0)

Files changed (1)

include/asm-arm/spinlock.h

 	__asm__ __volatile__(
 "1:	ldrex	%0, [%1]\n"
 "	teq	%0, #0\n"
+#ifdef CONFIG_CPU_32v6K
+"	wfene\n"
+#endif
 "	strexeq	%0, %2, [%1]\n"
 "	teqeq	%0, #0\n"
 "	bne	1b"
 	smp_mb();
 
 	__asm__ __volatile__(
-"	str	%1, [%0]"
+"	str	%1, [%0]\n"
+#ifdef CONFIG_CPU_32v6K
+"	mcr	p15, 0, %1, c7, c10, 4\n" /* DSB */
+"	sev"
+#endif
 	:
 	: "r" (&lock->lock), "r" (0)
 	: "cc");
 	__asm__ __volatile__(
 "1:	ldrex	%0, [%1]\n"
 "	teq	%0, #0\n"
+#ifdef CONFIG_CPU_32v6K
+"	wfene\n"
+#endif
 "	strexeq	%0, %2, [%1]\n"
 "	teq	%0, #0\n"
 "	bne	1b"
 	smp_mb();
 
 	__asm__ __volatile__(
-	"str	%1, [%0]"
+	"str	%1, [%0]\n"
+#ifdef CONFIG_CPU_32v6K
+"	mcr	p15, 0, %1, c7, c10, 4\n" /* DSB */
+"	sev\n"
+#endif
 	:
 	: "r" (&rw->lock), "r" (0)
 	: "cc");
 "1:	ldrex	%0, [%2]\n"
 "	adds	%0, %0, #1\n"
 "	strexpl	%1, %0, [%2]\n"
+#ifdef CONFIG_CPU_32v6K
+"	wfemi\n"
+#endif
 "	rsbpls	%0, %1, #0\n"
 "	bmi	1b"
 	: "=&r" (tmp), "=&r" (tmp2)
 "	strex	%1, %0, [%2]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
+#ifdef CONFIG_CPU_32v6K
+"\n	cmp	%0, #0\n"
+"	mcreq   p15, 0, %0, c7, c10, 4\n"
+"	seveq"
+#endif
 	: "=&r" (tmp), "=&r" (tmp2)
 	: "r" (&rw->lock)
 	: "cc");