1. spencercw
  2. gb_emulator

Commits

spencercw  committed 09ba6a9

Implement RR (HL).

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  • Parent commits 8a625fb
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Files changed (2)

File gb_emulator/gb_cpu_opcodes.cpp.inc

View file
 		}
 		break;
 	case RR_MHL:  /* RR (HL) */
-		clog << hex << setfill('0')
-		     << "RR (HL) -- not implemented (PC: 0x" << setw(4) << pc - 2 << ")\n";
-		exit(1);
+#ifdef DEBUG
+	if (showOps)
+		clog << hex << setfill('0') << setw(4) << pc - 2 << " RR (HL)\n";
+#endif
+		cycles -= 4;
+		{
+			uint8_t val = gb_.mem_.read(r.r16[HL]);
+			bool carry = val & 0x01;
+			val = (val >> 1) | (r.r8[F] & CF ? 0x80 : 0);
+			r.r8[F] =
+				(val ? 0 : Z) |
+				(carry ? CF : 0);
+			gb_.mem_.write(r.r16[HL], val);
+		}
+		break;
 	case SLA_A:  /* SLA A */
 #ifdef DEBUG
 	if (showOps)

File gb_emulator/ops.txt

View file
 cb1b RR_E       'RR E'               0 2 1 E:E:E:E
 cb1c RR_H       'RR H'               0 2 1 H:H:H:H
 cb1d RR_L       'RR L'               0 2 1 L:L:L:L
-cb1e RR_MHL     'RR (HL)'            0 4 0
+cb1e RR_MHL     'RR (HL)'            0 4 1
+{
+	uint8_t val = gb_.mem_.read(r.r16[HL]);
+	bool carry = val & 0x01;
+	val = (val >> 1) | (r.r8[F] & CF ? 0x80 : 0);
+	r.r8[F] =
+		(val ? 0 : Z) |
+		(carry ? CF : 0);
+	gb_.mem_.write(r.r16[HL], val);
+}
 
 ; SLA rm
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