Commits

spencercw committed 49d9e8e

#37 Implement srl [hl] and sra [hl].

These were the last two non-implemented instructions.

Comments (0)

Files changed (2)

gb_emulator/gb_cpu_opcodes.cpp.inc

 		}
 		break;
 	case SRA_MHL:
-		clog << hex << setfill('0')
-		     << 0xcb2e << " -- not implemented (PC: 0x" << setw(4) << pc - 2 << ")\n";
-		exit(1);
+		cycles -= 4;
+		{
+			uint8_t val = gb_.mem_.read(r.r16[HL]);
+			bool carry = val & 0x01;
+			val = val >> 1 | (val & 0x80);
+			gb_.mem_.write(r.r16[HL], val);
+			r.r8[F] =
+				(val ? 0 : Z) |
+				(carry ? CF : 0);
+		}
+		break;
 	case SRL_A:
 		cycles -= 2;
 		{
 		}
 		break;
 	case SRL_MHL:
-		clog << hex << setfill('0')
-		     << 0xcb3e << " -- not implemented (PC: 0x" << setw(4) << pc - 2 << ")\n";
-		exit(1);
+		cycles -= 4;
+		{
+			uint8_t val = gb_.mem_.read(r.r16[HL]);
+			bool carry = val & 0x01;
+			val >>= 1;
+			gb_.mem_.write(r.r16[HL], val);
+			r.r8[F] =
+				(val ? 0 : Z) |
+				(carry ? CF : 0);
+		}
+		break;
 	case BIT_0_A:
 		cycles -= 2;
 		r.r8[F] =

gb_emulator/ops.txt

 cb2b SRA_E      'sra e'              0 2 1 E:E:E:E:E
 cb2c SRA_H      'sra h'              0 2 1 H:H:H:H:H
 cb2d SRA_L      'sra l'              0 2 1 L:L:L:L:L
-cb2e SRA_MHL    'sra [hl]'           0 4 0
+cb2e SRA_MHL    'sra [hl]'           0 4 1
+{
+	uint8_t val = gb_.mem_.read(r.r16[HL]);
+	bool carry = val & 0x01;
+	val = val >> 1 | (val & 0x80);
+	gb_.mem_.write(r.r16[HL], val);
+	r.r8[F] =
+		(val ? 0 : Z) |
+		(carry ? CF : 0);
+}
 
 ; srl rm
 >
 cb3b SRL_E      'srl e'              0 2 1 E:E:E
 cb3c SRL_H      'srl h'              0 2 1 H:H:H
 cb3d SRL_L      'srl l'              0 2 1 L:L:L
-cb3e SRL_MHL    'srl [hl]'           0 4 0
+cb3e SRL_MHL    'srl [hl]'           0 4 1
+{
+	uint8_t val = gb_.mem_.read(r.r16[HL]);
+	bool carry = val & 0x01;
+	val >>= 1;
+	gb_.mem_.write(r.r16[HL], val);
+	r.r8[F] =
+		(val ? 0 : Z) |
+		(carry ? CF : 0);
+}
 
 ; ...