1. Stanislav Sedov
  2. valgrind-freebsd

Commits

Stanislav Sedov  committed 055db88

- Update to 3.8.1.

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  • Parent commits 80a3abd
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File Makefile.am

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 	README_MISSING_SYSCALL_OR_IOCTL \
 	README.s390 \
 	README.android \
+	README.android_emulator \
 	README.mips \
 	NEWS.old \
 	valgrind.pc.in \
 	valgrind.spec.in \
-	valgrind.spec
+	valgrind.spec \
+	autogen.sh
 
 dist_noinst_SCRIPTS = \
 	vg-in-place

File NEWS

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+
+Release 3.8.1 (19 September 2012)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+3.8.1 is a bug fix release.  It fixes some assertion failures in 3.8.0
+that occur moderately frequently in real use cases, adds support for
+some missing instructions on ARM, and fixes a deadlock condition on
+MacOSX.  If you package or deliver 3.8.0 for others to use, you might
+want to consider upgrading to 3.8.1 instead.
+
+The following bugs have been fixed or resolved.  Note that "n-i-bz"
+stands for "not in bugzilla" -- that is, a bug that was reported to us
+but never got a bugzilla entry.  We encourage you to file bugs in
+bugzilla (https://bugs.kde.org/enter_bug.cgi?product=valgrind) rather
+than mailing the developers (or mailing lists) directly -- bugs that
+are not entered into bugzilla tend to get forgotten about or ignored.
+
+To see details of a given bug, visit
+  https://bugs.kde.org/show_bug.cgi?id=XXXXXX
+where XXXXXX is the bug number as listed below.
+
+284004  == 301281
+289584  Unhandled instruction: 0xF 0x29 0xE5 (MOVAPS)
+295808  amd64->IR: 0xF3 0xF 0xBC 0xC0 (TZCNT)
+298281  wcslen causes false(?) uninitialised value warnings
+301281  valgrind hangs on OS X when the process calls system()
+304035  disInstr(arm): unhandled instruction 0xE1023053
+304867  implement MOVBE instruction in x86 mode
+304980  Assertion 'lo <= hi' failed in vgModuleLocal_find_rx_mapping
+305042  amd64: implement 0F 7F encoding of movq between two registers
+305199  ARM: implement QDADD and QDSUB
+305321  amd64->IR: 0xF 0xD 0xC (prefetchw)
+305513  killed by fatal signal: SIGSEGV
+305690  DRD reporting invalid semaphore when sem_trywait fails
+305926  Invalid alignment checks for some AVX instructions
+306297  disInstr(thumb): unhandled instruction 0xE883 0x000C
+306310  3.8.0 release tarball missing some files
+306612  RHEL 6 glibc-2.X default suppressions need /lib*/libc-*patterns
+306664  vex amd64->IR: 0x66 0xF 0x3A 0x62 0xD1 0x46 0x66 0xF
+n-i-bz  shmat of a segment > 4Gb does not work 
+n-i-bz  simulate_control_c script wrong USR1 signal number on mips
+n-i-bz  vgdb ptrace calls wrong on mips [...]
+n-i-bz  Fixes for more MPI false positives
+n-i-bz  exp-sgcheck's memcpy causes programs to segfault
+n-i-bz  OSX build w/ clang: asserts at startup
+n-i-bz  Incorrect undef'dness prop for Iop_DPBtoBCD and Iop_BCDtoDPB
+n-i-bz  fix a couple of union tag-vs-field mixups
+n-i-bz  OSX: use __NR_poll_nocancel rather than __NR_poll
+
+The following bugs were fixed in 3.8.0 but not listed in this NEWS
+file at the time:
+
+254088  Valgrind should know about UD2 instruction
+301280  == 254088
+301902  == 254088
+304754  NEWS blows TeX's little mind
+
+(3.8.1.TEST2: 18 September 2012, vex r2537, valgrind r12994)
+(3.8.1:       18 September 2012, vex r2537, valgrind r12996)
+
+
 
 Release 3.8.0 (10 August 2012)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

File README.android

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 # different if /sdcard doesn't work on the device -- this is
 # a known cause of difficulties.
 
+# The below re-generates configure, Makefiles, ...
+# This is not needed if you start from a release tarball.
 ./autogen.sh
 
 # for ARM

File VEX/priv/guest_amd64_toIR.c

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             goto mmx_decode_failure;
          modrm = getUChar(delta);
          if (epartIsReg(modrm)) {
-            /* Fall through.  The assembler doesn't appear to generate
-               these. */
-            goto mmx_decode_failure;
+            delta++;
+            putMMXReg( eregLO3ofRM(modrm), getMMXReg(gregLO3ofRM(modrm)) );
+            DIP("movq %s, %s\n",
+                nameMMXReg(gregLO3ofRM(modrm)),
+                nameMMXReg(eregLO3ofRM(modrm)));
          } else {
             IRTemp addr = disAMode( &len, vbi, pfx, delta, dis_buf, 0 );
             delta += len;
          modrm = getUChar(delta);
          if (epartIsReg(modrm)) {
             /* fall through; awaiting test case */
+            putXMMReg( eregOfRexRM(pfx,modrm),
+                       getXMMReg( gregOfRexRM(pfx,modrm) ));
+            DIP("movaps %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+                                  nameXMMReg(eregOfRexRM(pfx,modrm)));
+            delta += 1;
          } else {
             addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
             gen_SEGV_if_not_16_aligned( addr );
             DIP("movaps %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
                                   dis_buf );
             delta += alen;
-            goto decode_success;
-         }
+         }
+         goto decode_success;
       }
       /* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */
       if (have66noF2noF3(pfx)
       DIP("%sphminposuw %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG));
    } else {
       addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
-      gen_SEGV_if_not_16_aligned(addr);
+      if (!isAvx)
+         gen_SEGV_if_not_16_aligned(addr);
       assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
       delta += alen;
       DIP("%sphminposuw %s,%s\n", mbV, dis_buf, nameXMMReg(rG));
       case 0x00:
       case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
       case 0x1A: case 0x38: case 0x3A: case 0x44: case 0x4A:
+      case 0x46:
          break;
       case 0x01: // the 16-bit character versions of the above
       case 0x03: case 0x09: case 0x0B: case 0x0D: case 0x13:
       DIP("ud2\n");
       return delta;
 
+   case 0x0D: /* 0F 0D /0 -- prefetch mem8 */
+              /* 0F 0D /1 -- prefetchw mem8 */
+      if (have66orF2orF3(pfx)) goto decode_failure;
+      modrm = getUChar(delta);
+      if (epartIsReg(modrm)) goto decode_failure;
+      if (gregLO3ofRM(modrm) != 0 && gregLO3ofRM(modrm) != 1)
+         goto decode_failure;
+      addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+      delta += alen;
+      switch (gregLO3ofRM(modrm)) {
+         case 0: DIP("prefetch %s\n", dis_buf); break;
+         case 1: DIP("prefetchw %s\n", dis_buf); break;
+         default: vassert(0); /*NOTREACHED*/
+      }
+      return delta;
+
    case 0x1F:
       if (haveF2orF3(pfx)) goto decode_failure;
       modrm = getUChar(delta);
       return delta;
 
    case 0xBC: /* BSF Gv,Ev */
-      if (haveF2orF3(pfx)) goto decode_failure;
+      if (haveF2(pfx)) goto decode_failure;
       delta = dis_bs_E_G ( vbi, pfx, sz, delta, True );
       return delta;
 
    case 0xBD: /* BSR Gv,Ev */
-      if (!haveF2orF3(pfx)) {
-         /* no-F2 no-F3 0F BD = BSR */
+      if (!haveF2orF3(pfx)
+          || (haveF3noF2(pfx)
+              && 0 == (archinfo->hwcaps & VEX_HWCAPS_AMD64_LZCNT))) {
+         /* no-F2 no-F3 0F BD = BSR
+                  or F3 0F BD = REP; BSR on older CPUs.  */
          delta = dis_bs_E_G ( vbi, pfx, sz, delta, False );
          return delta;
       }
                                            nameXMMReg(rV), nameXMMReg(rG));
          } else {
             addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
-            gen_SEGV_if_not_16_aligned( addr );
             assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
             imm8 = getUChar(delta+alen);
             delta += alen+1;
          } else {
             addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 
                              1/* imm8 is 1 byte after the amode */ );
-            gen_SEGV_if_not_16_aligned( addr );
             assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
             imm8 = (Int)getUChar(delta+alen);
             delta += alen+1;
       /* =-=-=-=-=-=-=-=-=- Jcond d32 -=-=-=-=-=-=-=-=-= */
 
       /* =-=-=-=-=-=-=-=-=- PREFETCH =-=-=-=-=-=-=-=-=-= */
-      case 0x0D: /* 0F 0D /0 -- prefetch mem8 */
-                 /* 0F 0D /1 -- prefetchw mem8 */
-         if (have66orF2orF3(pfx)) goto decode_failure;
-         modrm = getUChar(delta);
-         if (epartIsReg(modrm)) goto decode_failure;
-         if (gregLO3ofRM(modrm) != 0 && gregLO3ofRM(modrm) != 1)
-            goto decode_failure;
-
-         addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
-         delta += alen;
-
-         switch (gregLO3ofRM(modrm)) {
-            case 0: DIP("prefetch %s\n", dis_buf); break;
-            case 1: DIP("prefetchw %s\n", dis_buf); break;
-            default: vassert(0); /*NOTREACHED*/
-         }
-         break;
 
       /* =-=-=-=-=-=-=-=-=- RDTSC -=-=-=-=-=-=-=-=-=-=-= */
 

File VEX/priv/guest_arm_toIR.c

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      /* fall through */
    }
 
+   /* ------------------ qdadd<c> <Rd>,<Rm>,<Rn> ------------------- */
+   {
+     UInt regD = 99, regN = 99, regM = 99;
+     Bool gate = False;
+
+     if (isT) {
+        if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF090) {
+           regN = INSNT0(3,0);
+           regD = INSNT1(11,8);
+           regM = INSNT1(3,0);
+           if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+              gate = True;
+        }
+     } else {
+        if (INSNA(27,20) == BITS8(0,0,0,1,0,1,0,0) &&
+            INSNA(11,8)  == BITS4(0,0,0,0)         &&
+            INSNA(7,4)   == BITS4(0,1,0,1)) {
+           regD = INSNA(15,12);
+           regN = INSNA(19,16);
+           regM = INSNA(3,0);
+           if (regD != 15 && regN != 15 && regM != 15)
+              gate = True;
+        }
+     }
+
+     if (gate) {
+        IRTemp rNt   = newTemp(Ity_I32);
+        IRTemp rMt   = newTemp(Ity_I32);
+        IRTemp rN_d  = newTemp(Ity_I32);
+        IRTemp res_q = newTemp(Ity_I32);
+
+        assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+        assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+        or_into_QFLAG32(
+           signed_overflow_after_Add32(
+              binop(Iop_Add32, mkexpr(rNt), mkexpr(rNt)), rNt, rNt),
+           condT
+        );
+
+        assign(rN_d,  binop(Iop_QAdd32S, mkexpr(rNt), mkexpr(rNt)));
+        assign(res_q, binop(Iop_QAdd32S, mkexpr(rMt), mkexpr(rN_d)));
+        if (isT)
+           putIRegT( regD, mkexpr(res_q), condT );
+        else
+           putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+        or_into_QFLAG32(
+           signed_overflow_after_Add32(
+              binop(Iop_Add32, mkexpr(rMt), mkexpr(rN_d)), rMt, rN_d),
+           condT
+        );
+
+        DIP("qdadd%s r%u, r%u, r%u\n", nCC(conq),regD,regM,regN);
+        return True;
+     }
+     /* fall through */
+   }
+
    /* ------------------ qsub<c> <Rd>,<Rn>,<Rm> ------------------- */
    {
      UInt regD = 99, regN = 99, regM = 99;
      /* fall through */
    }
 
+   /* ------------------ qdsub<c> <Rd>,<Rm>,<Rn> ------------------- */
+   {
+     UInt regD = 99, regN = 99, regM = 99;
+     Bool gate = False;
+
+     if (isT) {
+        if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF0B0) {
+           regN = INSNT0(3,0);
+           regD = INSNT1(11,8);
+           regM = INSNT1(3,0);
+           if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+              gate = True;
+        }
+     } else {
+        if (INSNA(27,20) == BITS8(0,0,0,1,0,1,1,0) &&
+            INSNA(11,8)  == BITS4(0,0,0,0)         &&
+            INSNA(7,4)   == BITS4(0,1,0,1)) {
+           regD = INSNA(15,12);
+           regN = INSNA(19,16);
+           regM = INSNA(3,0);
+           if (regD != 15 && regN != 15 && regM != 15)
+              gate = True;
+        }
+     }
+
+     if (gate) {
+        IRTemp rNt   = newTemp(Ity_I32);
+        IRTemp rMt   = newTemp(Ity_I32);
+        IRTemp rN_d  = newTemp(Ity_I32);
+        IRTemp res_q = newTemp(Ity_I32);
+
+        assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+        assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+        or_into_QFLAG32(
+           signed_overflow_after_Add32(
+              binop(Iop_Add32, mkexpr(rNt), mkexpr(rNt)), rNt, rNt),
+           condT
+        );
+
+        assign(rN_d,  binop(Iop_QAdd32S, mkexpr(rNt), mkexpr(rNt)));
+        assign(res_q, binop(Iop_QSub32S, mkexpr(rMt), mkexpr(rN_d)));
+        if (isT)
+           putIRegT( regD, mkexpr(res_q), condT );
+        else
+           putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+        or_into_QFLAG32(
+           signed_overflow_after_Sub32(
+              binop(Iop_Sub32, mkexpr(rMt), mkexpr(rN_d)), rMt, rN_d),
+           condT
+        );
+
+        DIP("qdsub%s r%u, r%u, r%u\n", nCC(conq),regD,regM,regN);
+        return True;
+     }
+     /* fall through */
+   }
+
+   /* ------------------ uqsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
+   {
+     UInt regD = 99, regN = 99, regM = 99;
+     Bool gate = False;
+
+     if (isT) {
+        if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF050) {
+           regN = INSNT0(3,0);
+           regD = INSNT1(11,8);
+           regM = INSNT1(3,0);
+           if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+              gate = True;
+        }
+     } else {
+        if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,0) &&
+            INSNA(11,8)  == BITS4(1,1,1,1)         &&
+            INSNA(7,4)   == BITS4(0,1,1,1)) {
+           regD = INSNA(15,12);
+           regN = INSNA(19,16);
+           regM = INSNA(3,0);
+           if (regD != 15 && regN != 15 && regM != 15)
+             gate = True;
+        }
+     }
+
+     if (gate) {
+        IRTemp rNt   = newTemp(Ity_I32);
+        IRTemp rMt   = newTemp(Ity_I32);
+        IRTemp res_q = newTemp(Ity_I32);
+
+        assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+        assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+        assign(res_q, binop(Iop_QSub16Ux2, mkexpr(rNt), mkexpr(rMt)));
+        if (isT)
+           putIRegT( regD, mkexpr(res_q), condT );
+        else
+           putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+        DIP("uqsub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+        return True;
+     }
+     /* fall through */
+   }
+
+   /* ----------------- shadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
+   {
+     UInt regD = 99, regN = 99, regM = 99;
+     Bool gate = False;
+
+     if (isT) {
+        if (INSNT0(15,4) == 0xFA9 && (INSNT1(15,0) & 0xF0F0) == 0xF020) {
+           regN = INSNT0(3,0);
+           regD = INSNT1(11,8);
+           regM = INSNT1(3,0);
+           if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+              gate = True;
+        }
+     } else {
+        if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,1) &&
+            INSNA(11,8)  == BITS4(1,1,1,1)         &&
+            INSNA(7,4)   == BITS4(0,0,0,1)) {
+           regD = INSNA(15,12);
+           regN = INSNA(19,16);
+           regM = INSNA(3,0);
+           if (regD != 15 && regN != 15 && regM != 15)
+              gate = True;
+        }
+     }
+
+     if (gate) {
+        IRTemp rNt   = newTemp(Ity_I32);
+        IRTemp rMt   = newTemp(Ity_I32);
+        IRTemp res_q = newTemp(Ity_I32);
+
+        assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+        assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+        assign(res_q, binop(Iop_HAdd16Sx2, mkexpr(rNt), mkexpr(rMt)));
+        if (isT)
+           putIRegT( regD, mkexpr(res_q), condT );
+        else
+           putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+        DIP("shadd16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+        return True;
+     }
+     /* fall through */
+   }
+
+   /* ----------------- uhsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
+   {
+     UInt regD = 99, regN = 99, regM = 99;
+     Bool gate = False;
+
+     if (isT) {
+        if (INSNT0(15,4) == 0xFAC && (INSNT1(15,0) & 0xF0F0) == 0xF060) {
+           regN = INSNT0(3,0);
+           regD = INSNT1(11,8);
+           regM = INSNT1(3,0);
+           if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+              gate = True;
+        }
+     } else {
+        if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,1) &&
+            INSNA(11,8)  == BITS4(1,1,1,1)         &&
+            INSNA(7,4)   == BITS4(1,1,1,1)) {
+           regD = INSNA(15,12);
+           regN = INSNA(19,16);
+           regM = INSNA(3,0);
+           if (regD != 15 && regN != 15 && regM != 15)
+              gate = True;
+        }
+     }
+
+     if (gate) {
+        IRTemp rNt   = newTemp(Ity_I32);
+        IRTemp rMt   = newTemp(Ity_I32);
+        IRTemp res_q = newTemp(Ity_I32);
+
+        assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+        assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+        assign(res_q, binop(Iop_HSub8Ux4, mkexpr(rNt), mkexpr(rMt)));
+        if (isT)
+           putIRegT( regD, mkexpr(res_q), condT );
+        else
+           putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+        DIP("uhsub8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+        return True;
+     }
+     /* fall through */
+   }
+
+   /* ----------------- uhsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
+   {
+     UInt regD = 99, regN = 99, regM = 99;
+     Bool gate = False;
+
+     if (isT) {
+        if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF060) {
+           regN = INSNT0(3,0);
+           regD = INSNT1(11,8);
+           regM = INSNT1(3,0);
+           if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+              gate = True;
+        }
+     } else {
+        if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,1) &&
+            INSNA(11,8)  == BITS4(1,1,1,1)         &&
+            INSNA(7,4)   == BITS4(0,1,1,1)) {
+           regD = INSNA(15,12);
+           regN = INSNA(19,16);
+           regM = INSNA(3,0);
+           if (regD != 15 && regN != 15 && regM != 15)
+              gate = True;
+        }
+     }
+
+     if (gate) {
+        IRTemp rNt   = newTemp(Ity_I32);
+        IRTemp rMt   = newTemp(Ity_I32);
+        IRTemp res_q = newTemp(Ity_I32);
+
+        assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+        assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+        assign(res_q, binop(Iop_HSub16Ux2, mkexpr(rNt), mkexpr(rMt)));
+        if (isT)
+           putIRegT( regD, mkexpr(res_q), condT );
+        else
+           putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+        DIP("uhsub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+        return True;
+     }
+     /* fall through */
+   }
+
    /* ---------- Doesn't match anything. ---------- */
    return False;
 
          if (rN == 15)                       valid = False;
          if (popcount32(regList) < 2)        valid = False;
          if (bW == 1 && (regList & (1<<rN))) valid = False;
-         if (regList & (1<<rN)) {
-            UInt i;
-            /* if Rn is in the list, then it must be the
-               lowest numbered entry */
-            for (i = 0; i < rN; i++) {
-               if (regList & (1<<i))
-                  valid = False;
-            }
-         }
       }
 
       if (valid) {

File VEX/priv/guest_generic_x87.c

View file
  • Ignore whitespace
       case 0x00:
       case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
       case 0x1A: case 0x38: case 0x3A: case 0x44: case 0x4A:
+      case 0x46:
          break;
       default:
          return False;
       return True;
    }
 
+   /*----------------------------------------*/
+   /*-- ranges, signed byte data           --*/
+   /*----------------------------------------*/
+
+   if (agg == 1/*ranges*/
+       && fmt == 2/*sb*/) {
+
+      /* argL: string,  argR: range-pairs */
+      UInt   ri, si;
+      Char*  argL    = (Char*)argLV;
+      Char*  argR    = (Char*)argRV;
+      UInt   boolRes = 0;
+      UInt   validL  = ~(zmaskL | -zmaskL);  // not(left(zmaskL))
+      UInt   validR  = ~(zmaskR | -zmaskR);  // not(left(zmaskR))
+      for (si = 0; si < 16; si++) {
+         if ((validL & (1 << si)) == 0)
+            // run off the end of the string
+            break;
+         UInt m = 0;
+         for (ri = 0; ri < 16; ri += 2) {
+            if ((validR & (3 << ri)) != (3 << ri)) break;
+            if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) { 
+               m = 1; break;
+            }
+         }
+         boolRes |= (m << si);
+      }
+
+      // boolRes is "pre-invalidated"
+      UInt intRes1 = boolRes & 0xFFFF;
+
+      // generate I-format output
+      compute_PCMPxSTRx_gen_output(
+         resV, resOSZACP,
+         intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+      );
+
+      return True;
+   }
+
    return False;
 }
 

File VEX/priv/guest_x86_toIR.c

View file
  • Ignore whitespace
    return False;
 }
 
+static IRTemp math_BSWAP ( IRTemp t1, IRType ty )
+{
+   IRTemp t2 = newTemp(ty);
+   if (ty == Ity_I32) {
+      assign( t2,
+         binop(
+            Iop_Or32,
+            binop(Iop_Shl32, mkexpr(t1), mkU8(24)),
+            binop(
+               Iop_Or32,
+               binop(Iop_And32, binop(Iop_Shl32, mkexpr(t1), mkU8(8)),
+                                mkU32(0x00FF0000)),
+               binop(Iop_Or32,
+                     binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(8)),
+                                      mkU32(0x0000FF00)),
+                     binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(24)),
+                                      mkU32(0x000000FF) )
+            )))
+      );
+      return t2;
+   }
+   if (ty == Ity_I16) {
+      assign(t2, 
+             binop(Iop_Or16,
+                   binop(Iop_Shl16, mkexpr(t1), mkU8(8)),
+                   binop(Iop_Shr16, mkexpr(t1), mkU8(8)) ));
+      return t2;
+   }
+   vassert(0);
+   /*NOTREACHED*/
+   return IRTemp_INVALID;
+}
 
 /*------------------------------------------------------------*/
 /*--- Disassemble a single instruction                     ---*/
       );
       goto decode_success;
    }
+   
+   /* 0F 38 F0 = MOVBE m16/32(E), r16/32(G) */
+   /* 0F 38 F1 = MOVBE r16/32(G), m16/32(E) */
+   if ((sz == 2 || sz == 4)
+       && insn[0] == 0x0F && insn[1] == 0x38
+       && (insn[2] == 0xF0 || insn[2] == 0xF1)
+       && !epartIsReg(insn[3])) {
+
+      modrm = insn[3];
+      addr = disAMode(&alen, sorb, delta + 3, dis_buf);
+      delta += 3 + alen;
+      ty = szToITy(sz);
+      IRTemp src = newTemp(ty);
+
+      if (insn[2] == 0xF0) { /* LOAD */
+         assign(src, loadLE(ty, mkexpr(addr)));
+         IRTemp dst = math_BSWAP(src, ty);
+         putIReg(sz, gregOfRM(modrm), mkexpr(dst));
+         DIP("movbe %s,%s\n", dis_buf, nameIReg(sz, gregOfRM(modrm)));
+      } else { /* STORE */
+         assign(src, getIReg(sz, gregOfRM(modrm)));
+         IRTemp dst = math_BSWAP(src, ty);
+         storeLE(mkexpr(addr), mkexpr(dst));
+         DIP("movbe %s,%s\n", nameIReg(sz, gregOfRM(modrm)), dis_buf);
+      }
+      goto decode_success;
+   }
 
    /* ---------------------------------------------------- */
    /* --- end of the SSSE3 decoder.                    --- */
       for the rest, it means REP) */
    case 0xF3: { 
       Addr32 eip_orig = guest_EIP_bbstart + delta_start;
-      if (sorb != 0) goto decode_failure;
       abyte = getIByte(delta); delta++;
 
       if (abyte == 0x66) { sz = 2; abyte = getIByte(delta); delta++; }
 
+      if (sorb != 0 && abyte != 0x0F) goto decode_failure;
+
       switch (abyte) {
+      case 0x0F:
+         switch (getIByte(delta)) {
+         /* On older CPUs, TZCNT behaves the same as BSF.  */
+         case 0xBC: /* REP BSF Gv,Ev */
+            delta = dis_bs_E_G ( sorb, sz, delta + 1, True );
+            break;
+         /* On older CPUs, LZCNT behaves the same as BSR.  */
+         case 0xBD: /* REP BSR Gv,Ev */
+            delta = dis_bs_E_G ( sorb, sz, delta + 1, False );
+            break;
+         default:
+            goto decode_failure;
+         }
+         break;
+
       case 0xA4: sz = 1;   /* REP MOVS<sz> */
       case 0xA5:
          dis_REP_op ( &dres, X86CondAlways, dis_MOVS, sz, eip_orig, 
       case 0xCE:
       case 0xCF: /* BSWAP %edi */
          /* AFAICS from the Intel docs, this only exists at size 4. */
-         vassert(sz == 4);
+         if (sz != 4) goto decode_failure;
+         
          t1 = newTemp(Ity_I32);
-         t2 = newTemp(Ity_I32);
          assign( t1, getIReg(4, opc-0xC8) );
-
-         assign( t2,
-            binop(Iop_Or32,
-               binop(Iop_Shl32, mkexpr(t1), mkU8(24)),
-            binop(Iop_Or32,
-               binop(Iop_And32, binop(Iop_Shl32, mkexpr(t1), mkU8(8)), 
-                                mkU32(0x00FF0000)),
-            binop(Iop_Or32,
-               binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(8)),
-                                mkU32(0x0000FF00)),
-               binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(24)),
-                                mkU32(0x000000FF) )
-            )))
-         );
+         t2 = math_BSWAP(t1, Ity_I32);
 
          putIReg(4, opc-0xC8, mkexpr(t2));
          DIP("bswapl %s\n", nameIReg(4, opc-0xC8));

File VEX/priv/host_arm_isel.c

View file
  • Ignore whitespace
             fn = &h_generic_calc_QAdd32S; break;
          case Iop_QSub32S:
             fn = &h_generic_calc_QSub32S; break;
+         case Iop_QSub16Ux2:
+            fn = &h_generic_calc_QSub16Ux2; break;
          default:
             break;
       }

File VEX/priv/host_s390_defs.c

View file
  • Ignore whitespace
    UInt r1    = hregNumber(insn->variant.bfp128_unop.dst_hi);
    UInt r2_hi = hregNumber(insn->variant.bfp128_unop.op_hi);
    UInt r2_lo = hregNumber(insn->variant.bfp128_unop.op_lo);
-   s390_round_t rounding_mode = insn->variant.bfp_binop.rounding_mode;
+   s390_round_t rounding_mode = insn->variant.bfp128_unop.rounding_mode;
 
    /* Paranoia */
    vassert(insn->size != 16);

File VEX/priv/host_s390_isel.c

View file
  • Ignore whitespace
 
       /* --------- UNARY OP --------- */
    case Iex_Unop: {
-      IRExpr *left = expr->Iex.Binop.arg1;
+      IRExpr *left = expr->Iex.Unop.arg;
       s390_bfp_unop_t bfpop;
       s390_round_t rounding_mode;
       HReg op_hi, op_lo, op, f12, f13, f14, f15;
       f14 = make_fpr(14);
       f15 = make_fpr(15);
 
-      switch (expr->Iex.Binop.op) {
+      switch (expr->Iex.Unop.op) {
       case Iop_NegF128:       bfpop = S390_BFP_NEG;          goto float128_opnd;
       case Iop_AbsF128:       bfpop = S390_BFP_ABS;          goto float128_opnd;
       case Iop_I32StoF128:    bfpop = S390_BFP_I32_TO_F128;  goto convert_int;

File VEX/priv/ir_defs.c

View file
  • Ignore whitespace
       }
       case Iex_Unop:
          tcExpr(bb,stmt, expr->Iex.Unop.arg, gWordTy );
-         typeOfPrimop(expr->Iex.Binop.op, 
+         typeOfPrimop(expr->Iex.Unop.op, 
                       &t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4);
          if (t_arg1 == Ity_INVALID || t_arg2 != Ity_INVALID
              || t_arg3 != Ity_INVALID || t_arg4 != Ity_INVALID)

File configure.in

View file
  • Ignore whitespace
 ##------------------------------------------------------------##
 
 # Process this file with autoconf to produce a configure script.
-AC_INIT([Valgrind],[3.8.0],[valgrind-users@lists.sourceforge.net])
+AC_INIT([Valgrind],[3.8.1],[valgrind-users@lists.sourceforge.net])
 AC_CONFIG_SRCDIR(coregrind/m_main.c)
 AC_CONFIG_HEADERS([config.h])
 AM_INIT_AUTOMAKE([foreign])

File coregrind/m_debuginfo/priv_storage.h

View file
  • Ignore whitespace
    if not found.  Binary search.  */
 extern Word ML_(search_one_fpotab) ( struct _DebugInfo* di, Addr ptr );
 
-/* Helper function for the most often needed searching for an rx mapping
-   containing the specified address range. */
+/* Helper function for the most often needed searching for an rx
+   mapping containing the specified address range.  The range must
+   fall entirely within the mapping to be considered to be within it.
+   Asserts if lo > hi; caller must ensure this doesn't happen. */
 extern struct _DebugInfoMapping* ML_(find_rx_mapping) ( struct _DebugInfo* di,
                                                         Addr lo, Addr hi );
 

File coregrind/m_debuginfo/readdwarf.c

View file
  • Ignore whitespace
             case 0x01: /* FORM_addr */      p += addr_size; break;
             case 0x03: /* FORM_block2 */    p += ML_(read_UShort)(p) + 2; break;
             case 0x04: /* FORM_block4 */    p += ML_(read_UInt)(p) + 4; break;
-            case 0x09: /* FORM_block */     p += read_leb128U( &p ); break;
+            case 0x09: /* FORM_block */     /* fallthrough */
+            case 0x18: /* FORM_exprloc */   { ULong block_len = read_leb128U( &p );
+                                              p += block_len; break; }
             case 0x0a: /* FORM_block1 */    p += *p + 1; break;
             case 0x0c: /* FORM_flag */      p++; break;
             case 0x0d: /* FORM_sdata */     read_leb128S( &p ); break;
             case 0x13: /* FORM_ref4 */      p += 4; break;
             case 0x14: /* FORM_ref8 */      p += 8; break;
             case 0x15: /* FORM_ref_udata */ read_leb128U( &p ); break;
-            case 0x18: /* FORM_exprloc */   p += read_leb128U( &p ); break;
             case 0x19: /* FORM_flag_present */break;
             case 0x20: /* FORM_ref_sig8 */  p += 8; break;
             case 0x1f20: /* FORM_GNU_ref_alt */ p += ui->dw64 ? 8 : 4; break;

File coregrind/m_debuginfo/readelf.c

View file
  • Ignore whitespace
    *sym_name_out   = sym_name;
    *sym_avma_out   = sym_svma; /* we will bias this shortly */
    *is_text_out    = True;
-   *sym_size_out   = (Int)sym->st_size;
    *sym_tocptr_out = 0; /* unknown/inapplicable */
    *from_opd_out   = False;
    *is_ifunc       = False;
+   /* Get the symbol size, but restrict it to fit in a signed 32 bit
+      int.  Also, deal with the stupid case of negative size by making
+      the size be 1.  Note that sym->st_size has type UWord,
+      effectively. */
+   { Word size_tmp = (Word)sym->st_size;
+     Word max_Int  = (1LL << 31) - 1;
+     if (size_tmp < 0)       size_tmp = 1;
+     if (size_tmp > max_Int) size_tmp = max_Int;
+     *sym_size_out = (Int)size_tmp;
+   }
+   /* After this point refer only to *sym_size_out and not to
+      sym->st_size. */
 
    /* Figure out if we're interested in the symbol.  Firstly, is it of
       the right flavour?  */
         &&
         (ELFXX_ST_TYPE(sym->st_info) == STT_FUNC 
          || ELFXX_ST_TYPE(sym->st_info) == STT_OBJECT
-#ifdef STT_GNU_IFUNC
+#        ifdef STT_GNU_IFUNC
          || ELFXX_ST_TYPE(sym->st_info) == STT_GNU_IFUNC
-#endif
+#        endif
         );
 
    /* Work out the svma and bias for each section as it will appear in
    if (!plausible
        && *is_text_out
        && ELFXX_ST_TYPE(sym->st_info) == STT_NOTYPE
-       && sym->st_size > 0
+       && *sym_size_out > 0
        && di->opd_present
        && di->opd_size > 0
        && *sym_avma_out >= di->opd_avma
       in /system/lib/libc.so: strlen strcmp strcpy memcmp memcpy
       in /system/bin/linker:  __dl_strcmp __dl_strlen
    */
-   if (sym->st_size == 0) {
+   if (*sym_size_out == 0) {
 #     if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
       *sym_size_out = 2048;
 #     else
          background. */
       Bool in_rx;
       vg_assert(di->fsm.have_rx_map);
+      /* This could actually wrap around and cause
+         ML_(find_rx_mapping) to assert.  But that seems so unlikely,
+         let's wait for it to happen before fixing it. */
       in_rx = (ML_(find_rx_mapping)(di, *sym_avma_out,
                                     *sym_avma_out + *sym_size_out) != NULL);
       if (in_text)

File coregrind/m_debuginfo/storage.c

View file
  • Ignore whitespace
 {
    static const Bool debug = False;
    DiLoc loc;
-   Int size = next - this;
+   UWord size = next - this;
 
    /* Ignore zero-sized locs */
    if (this == next) return;
        if (0)
        VG_(message)(Vg_DebugMsg, 
                     "warning: line info address range too large "
-                    "at entry %d: %d\n", entry, size);
+                    "at entry %d: %lu\n", entry, size);
        size = 1;
    }
 
+   /* At this point, we know that the original value for |size|, viz
+      |next - this|, will only still be used in the case where
+      |this| <u |next|, so it can't have underflowed.  Considering
+      that and the three checks that follow it, the following must
+      hold. */
+   vg_assert(size >= 1);
+   vg_assert(size <= MAX_LOC_SIZE);
+
    /* Rule out ones which are completely outside the r-x mapped area.
       See "Comment_Regarding_Text_Range_Checks" elsewhere in this file
       for background and rationale. */
    vg_assert(di->fsm.have_rx_map && di->fsm.have_rw_map);
-   if (ML_(find_rx_mapping)(di, this, next - 1) == NULL) {
+   if (ML_(find_rx_mapping)(di, this, this + size - 1) == NULL) {
        if (0)
           VG_(message)(Vg_DebugMsg, 
                        "warning: ignoring line info entry falling "
                        "outside current DebugInfo: %#lx %#lx %#lx %#lx\n",
                        di->text_avma, 
                        di->text_avma + di->text_size, 
-                       this, next-1);
+                       this, this + size - 1);
        return;
    }
 
    loc.dirname   = dirname;
 
    if (0) VG_(message)(Vg_DebugMsg, 
-		       "addLoc: addr %#lx, size %d, line %d, file %s\n",
+		       "addLoc: addr %#lx, size %lu, line %d, file %s\n",
 		       this,size,lineno,filename);
 
    addLoc ( di, &loc );

File coregrind/m_libcfile.c

View file
  • Ignore whitespace
    return True;
 }
 
-Int    VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout)
+Int VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout)
 {
    SysRes res;
+#  if defined(VGO_linux)
    res = VG_(do_syscall3)(__NR_poll, (UWord)fds, nfds, timeout);
+#  elif defined(VGO_darwin)
+   res = VG_(do_syscall3)(__NR_poll_nocancel, (UWord)fds, nfds, timeout);
+#  else
+#    error "Unknown OS"
+#  endif
    return sr_isError(res) ? -1 : sr_Res(res);
 }
 

File coregrind/m_main.c

View file
  • Ignore whitespace
    VG_(debugLog)(1, "main", "Checking current stack is plausible\n");
    { HChar* limLo  = (HChar*)(&VG_(interim_stack).bytes[0]);
      HChar* limHi  = limLo + sizeof(VG_(interim_stack));
-     HChar* aLocal = (HChar*)&limLo; /* any auto local will do */
-     /* "Apple clang version 4.0 (tags/Apple/clang-421.0.57) (based on
-         LLVM 3.1svn)" appears to miscompile the following check,
-         causing run to abort at this point (in 64-bit mode) even
-         though aLocal is within limLo .. limHi.  Try building with
-         gcc instead. */
+     HChar* volatile 
+            aLocal = (HChar*)&limLo; /* any auto local will do */
+     /* Re "volatile": Apple clang version 4.0
+        (tags/Apple/clang-421.0.57) (based on LLVM 3.1svn)" appeared
+        to miscompile the following check, causing run to abort at
+        this point (in 64-bit mode) even though aLocal is within limLo
+        .. limHi.  But in fact clang is within its rights to do
+        strange things here.  "The reason is that the comparisons
+        aLocal < limLo and aLocal >= limHi cause undefined behaviour
+        (according to c99 6.5.8) because they compare pointers that do
+        not point into the same aggregate."  Adding "volatile" appears
+        to fix it because "The compiler would have to prove that there
+        is undefined behavior in order to exploit it.  But as a
+        volatile variable can change its value in ways invisible to
+        the compiler, the compiler must make the conservative
+        assumption that it points into the same aggregate as the other
+        pointer its compared against.  I.e. the behaviour is possibly
+        defined." (Analysis by Florian Krohm). */
      if (aLocal < limLo || aLocal >= limHi) {
         /* something's wrong.  Stop. */
         VG_(debugLog)(0, "main", "Root stack %p to %p, a local %p\n",

File coregrind/m_syswrap/syswrap-darwin.c

View file
  • Ignore whitespace
 #include "pub_core_debuglog.h"
 #include "pub_core_debuginfo.h"    // VG_(di_notify_*)
 #include "pub_core_transtab.h"     // VG_(discard_translations)
-#include "pub_tool_gdbserver.h"    // VG_(gdbserver)
 #include "pub_core_libcbase.h"
 #include "pub_core_libcassert.h"
 #include "pub_core_libcfile.h"
    /* Ok.  So let's give it a try. */
    VG_(debugLog)(1, "syswrap", "Posix_spawn of %s\n", (Char*)ARG2);
 
-   // Terminate gdbserver if it is active.
-   if (VG_(clo_vgdb)  != Vg_VgdbNo) {
-      // If the child will not be traced, we need to terminate gdbserver
-      // to cleanup the gdbserver resources (e.g. the FIFO files).
-      // If child will be traced, we also terminate gdbserver: the new 
-      // Valgrind will start a fresh gdbserver after exec.
-      VG_(gdbserver) (tid);
-   }
+   /* posix_spawn on Darwin is combining the fork and exec in one syscall.
+      So, we should not terminate gdbserver : this is still the parent
+      running, which will terminate its gdbserver when exiting.
+      If the child process is traced, it will start a fresh gdbserver
+      after posix_spawn. */
 
    // Set up the child's exe path.
    //
 POST(posix_spawn)
 {
    vg_assert(SUCCESS);
-   //POST_MEM_WRITE( ARG1, sizeof(vki_pid_t) );
+   if (ARG1 != 0) {
+      POST_MEM_WRITE( ARG1, sizeof(vki_pid_t) );
+   }
 }
 
 

File coregrind/m_syswrap/syswrap-generic.c

View file
  • Ignore whitespace
 /* ------ */
 
 static
-UInt get_shm_size ( Int shmid )
+SizeT get_shm_size ( Int shmid )
 {
 #ifdef __NR_shmctl
 #  ifdef VKI_IPC_64
    if (sr_isError(__res))
       return 0;
  
-   return buf.shm_segsz;
+   return (SizeT) buf.shm_segsz;
 }
 
 UWord
                              UWord arg0, UWord arg1, UWord arg2 )
 {
    /* void *shmat(int shmid, const void *shmaddr, int shmflg); */
-   UInt  segmentSize = get_shm_size ( arg0 );
+   SizeT  segmentSize = get_shm_size ( arg0 );
    UWord tmp;
    Bool  ok;
    if (arg1 == 0) {
                               UWord res,
                               UWord arg0, UWord arg1, UWord arg2 )
 {
-   UInt segmentSize = VG_PGROUNDUP(get_shm_size(arg0));
+   SizeT segmentSize = VG_PGROUNDUP(get_shm_size(arg0));
    if ( segmentSize > 0 ) {
       UInt prot = VKI_PROT_READ|VKI_PROT_WRITE;
       Bool d;

File coregrind/vgdb.c

View file
  • Ignore whitespace
 #elif defined(VGA_s390x)
    sp = user_mod.regs.gprs[15];
 #elif defined(VGA_mips32)
-   sp = user_mod.regs[29];
+   sp = user_mod.regs[29*2];
 #else
    I_die_here : (sp) architecture missing in vgdb.c
 #endif
 #elif defined(VGA_s390x)
       XERROR(0, "(fn32) s390x has no 32bits implementation");
 #elif defined(VGA_mips32)
-      /* put check arg in register 0 */
-      user_mod.regs[4] = check;
+      /* put check arg in register 4 */
+      user_mod.regs[4*2] = check;
+      user_mod.regs[4*2+1] = 0xffffffff; // sign extend $a0
+      /* This sign extension is needed when vgdb 32 bits runs
+         on a 64 bits OS. */
       /* put NULL return address in ra */
-      user_mod.regs[31] = bad_return;
-      user_mod.regs[25] = shared32->invoke_gdbserver;
+      user_mod.regs[31*2] = bad_return;
+      user_mod.regs[31*2+1] = 0;
+      user_mod.regs[34*2] = shared32->invoke_gdbserver;
+      user_mod.regs[34*2+1] = 0;
+      user_mod.regs[25*2] = shared32->invoke_gdbserver;
+      user_mod.regs[25*2+1] = 0;
 #else
       I_die_here : architecture missing in vgdb.c
 #endif

File drd/drd_semaphore.c

View file
  • Ignore whitespace
 
 /**
  * Called after sem_wait() finished.
- * @note Do not rely on the value of 'waited' -- some glibc versions do
- *       not set it correctly.
+ * @note Some C libraries do not set the 'waited' value correctly.
  */
 void DRD_(semaphore_post_wait)(const DrdThreadId tid, const Addr semaphore,
                                const Bool waited)
    struct semaphore_info* p;
    Segment* sg;
 
+   tl_assert(waited == 0 || waited == 1);
    p = semaphore_get(semaphore);
    if (s_trace_semaphore)
-      DRD_(trace_msg)("[%d] sem_wait      0x%lx value %u -> %u",
+      DRD_(trace_msg)("[%d] sem_wait      0x%lx value %u -> %u%s",
                       DRD_(thread_get_running_tid)(), semaphore,
-                      p ? p->value : 0, p ? p->value - 1 : 0);
+                      p ? p->value : 0, p ? p->value - waited : 0,
+		      waited ? "" : " (did not wait)");
 
-   if (p)
-   {
+   if (p) {
       p->waiters--;
-      p->value--;
+      p->value -= waited;
    }
 
    /*
       return;
    }
 
+   if (!waited)
+      return;
+
    if (p->waits_to_skip > 0)
       p->waits_to_skip--;
    else

File exp-sgcheck/h_intercepts.c

View file
  • Ignore whitespace
 
 #define MEMCPY(soname, fnname) \
    void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
-            ( void *dst, const void *src, SizeT sz ); \
+            ( void *dst, const void *src, SizeT len ); \
    void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
-            ( void *dest, const void *src, SizeT sz ) \
+            ( void *dst, const void *src, SizeT len ) \
    { \
-   const UChar*  s  = (const UChar*)src; \
-         UChar*  d  =       (UChar*)dest; \
-   const UWord*  sW = (const UWord*)src; \
-         UWord*  dW =       (UWord*)dest; \
-   const UWord   al = sizeof(UWord)-1; \
-   \
-   if (0 == (((UWord)dW) & al) && 0 == (((UWord)sW) & al)) { \
-      while (sz >= 4 * sizeof(UWord)) { \
-         dW[0] = sW[0]; \
-         dW[1] = sW[1]; \
-         dW[2] = sW[2]; \
-         dW[3] = sW[3]; \
-         sz -= 4 * sizeof(UWord); \
-         dW += 4; \
-         sW += 4; \
+      const Addr WS = sizeof(UWord); /* 8 or 4 */ \
+      const Addr WM = WS - 1;        /* 7 or 3 */ \
+      \
+      if (len > 0) { \
+         if (dst < src) { \
+         \
+            /* Copying backwards. */ \
+            SizeT n = len; \
+            Addr  d = (Addr)dst; \
+            Addr  s = (Addr)src; \
+            \
+            if (((s^d) & WM) == 0) { \
+               /* s and d have same UWord alignment. */ \
+               /* Pull up to a UWord boundary. */ \
+               while ((s & WM) != 0 && n >= 1) \
+                  { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \
+               /* Copy UWords. */ \
+               while (n >= WS) \
+                  { *(UWord*)d = *(UWord*)s; s += WS; d += WS; n -= WS; } \
+               if (n == 0) \
+                  return dst; \
+            } \
+            if (((s|d) & 1) == 0) { \
+               /* Both are 16-aligned; copy what we can thusly. */ \
+               while (n >= 2) \
+                  { *(UShort*)d = *(UShort*)s; s += 2; d += 2; n -= 2; } \
+            } \
+            /* Copy leftovers, or everything if misaligned. */ \
+            while (n >= 1) \
+               { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \
+         \
+         } else if (dst > src) { \
+         \
+            SizeT n = len; \
+            Addr  d = ((Addr)dst) + n; \
+            Addr  s = ((Addr)src) + n; \
+            \
+            /* Copying forwards. */ \
+            if (((s^d) & WM) == 0) { \
+               /* s and d have same UWord alignment. */ \
+               /* Back down to a UWord boundary. */ \
+               while ((s & WM) != 0 && n >= 1) \
+                  { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \
+               /* Copy UWords. */ \
+               while (n >= WS) \
+                  { s -= WS; d -= WS; *(UWord*)d = *(UWord*)s; n -= WS; } \
+               if (n == 0) \
+                  return dst; \
+            } \
+            if (((s|d) & 1) == 0) { \
+               /* Both are 16-aligned; copy what we can thusly. */ \
+               while (n >= 2) \
+                  { s -= 2; d -= 2; *(UShort*)d = *(UShort*)s; n -= 2; } \
+            } \
+            /* Copy leftovers, or everything if misaligned. */ \
+            while (n >= 1) \
+               { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \
+            \
+         } \
       } \
-      if (sz == 0) \
-         return dest; \
-      while (sz >= 1 * sizeof(UWord)) { \
-         dW[0] = sW[0]; \
-         sz -= 1 * sizeof(UWord); \
-         dW += 1; \
-         sW += 1; \
-      } \
-      if (sz == 0) \
-         return dest; \
-      s = (const UChar*)sW; \
-      d = (UChar*)dW; \
-   } \
-   \
-   while (sz--) \
-      *d++ = *s++; \
-   \
-   return dest; \
+      \
+      return dst; \
    }
 
 MEMCPY(VG_Z_LIBC_SONAME, memcpy)

File gdbserver_tests/simulate_control_c

View file
  • Ignore whitespace
    sleep 1
  done
  sleep $SLEEP
- kill -10 $VGDBPID) &
+ kill -s USR1 $VGDBPID) &

File memcheck/mc_replace_strmem.c

View file
  • Ignore whitespace
    20340 STRSPN
    20350 STRCASESTR
    20360 MEMRCHR
+   20370 WCSLEN
 */
 
 
 
 #if defined(VGO_linux)
  MEMMOVE(VG_Z_LIBC_SONAME, memmove)
+ MEMMOVE(VG_Z_LIBC_SONAME, __GI_memmove)
 
 #elif defined(VGO_darwin)
 # if DARWIN_VERS <= DARWIN_10_6
 #endif
 
 
+/*---------------------- wcslen ----------------------*/
+
+// This is a wchar_t equivalent to strlen.  Unfortunately
+// we don't have wchar_t available here, but it looks like
+// a 32 bit int on Linux.  I don't know if that is also
+// valid on MacOSX.
+
+#define WCSLEN(soname, fnname) \
+   SizeT VG_REPLACE_FUNCTION_EZU(20370,soname,fnname) \
+      ( const UInt* str ); \
+   SizeT VG_REPLACE_FUNCTION_EZU(20370,soname,fnname) \
+      ( const UInt* str )  \
+   { \
+      SizeT i = 0; \
+      while (str[i] != 0) i++; \
+      return i; \
+   }
+
+#if defined(VGO_linux)
+ WCSLEN(VG_Z_LIBC_SONAME,          wcslen)
+
+#elif defined(VGO_darwin)
+
+#endif
+
+
 /*------------------------------------------------------------*/
 /*--- Improve definedness checking of process environment  ---*/
 /*------------------------------------------------------------*/

File memcheck/mc_translate.c

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  • Ignore whitespace
       case Iop_HSub16Sx2:
       case Iop_QAdd16Sx2:
       case Iop_QSub16Sx2:
+      case Iop_QSub16Ux2:
          return binary16Ix2(mce, vatom1, vatom2);
 
       case Iop_Add8x4:
       case Iop_D32toD64:
       case Iop_ExtractExpD64:    /* D64  -> I64 */
       case Iop_ExtractExpD128:   /* D128 -> I64 */
+      case Iop_DPBtoBCD:
+      case Iop_BCDtoDPB:
          return mkPCastTo(mce, Ity_I64, vatom);
 
       case Iop_D64toD128:
       case Iop_ReinterpF32asI32:
       case Iop_ReinterpI64asD64:
       case Iop_ReinterpD64asI64:
-      case Iop_DPBtoBCD:
-      case Iop_BCDtoDPB:
       case Iop_NotV256:
       case Iop_NotV128:
       case Iop_Not64:

File memcheck/tests/amd64/insn_basic.stderr.exp

View file
  • Ignore whitespace
-../../../none/tests/amd64/insn_basic.stderr.exp

File memcheck/tests/amd64/insn_basic.stdout.exp

View file
  • Ignore whitespace
-../../../none/tests/amd64/insn_basic.stdout.exp
+adcb_1 ... ok
+adcb_2 ... ok
+adcb_3 ... ok
+adcb_4 ... ok
+adcb_5 ... ok
+adcb_6 ... ok
+adcb_7 ... ok
+adcb_8 ... ok
+adcb_9 ... ok
+adcb_10 ... ok
+adcw_1 ... ok
+adcw_2 ... ok
+adcw_3 ... ok
+adcw_4 ... ok
+adcw_5 ... ok
+adcw_6 ... ok
+adcw_7 ... ok
+adcw_8 ... ok
+adcw_9 ... ok
+adcw_10 ... ok
+adcw_11 ... ok
+adcw_12 ... ok
+adcl_1 ... ok
+adcl_2 ... ok
+adcl_3 ... ok
+adcl_4 ... ok
+adcl_5 ... ok
+adcl_6 ... ok
+adcl_7 ... ok
+adcl_8 ... ok
+adcl_9 ... ok
+adcl_10 ... ok
+adcl_11 ... ok
+adcl_12 ... ok
+adcq_1 ... ok
+adcq_2 ... ok
+adcq_3 ... ok
+adcq_4 ... ok
+adcq_5 ... ok
+adcq_6 ... ok
+adcq_7 ... ok
+adcq_8 ... ok
+adcq_9 ... ok
+adcq_10 ... ok
+adcq_11 ... ok
+adcq_12 ... ok
+addb_1 ... ok
+addb_2 ... ok
+addb_3 ... ok
+addb_4 ... ok
+addb_5 ... ok
+addb_6 ... ok
+addw_1 ... ok
+addw_2 ... ok
+addw_3 ... ok
+addw_4 ... ok
+addw_5 ... ok
+addw_6 ... ok
+addw_7 ... ok
+addl_1 ... ok
+addl_2 ... ok
+addl_3 ... ok
+addl_4 ... ok
+addl_5 ... ok
+addl_6 ... ok
+addl_7 ... ok
+addq_1 ... ok
+addq_2 ... ok
+addq_3 ... ok
+addq_4 ... ok
+addq_5 ... ok
+addq_6 ... ok
+addq_7 ... ok
+andb_1 ... ok
+andb_2 ... ok
+andb_3 ... ok
+andb_4 ... ok
+andb_5 ... ok
+andb_6 ... ok
+andw_1 ... ok
+andw_2 ... ok
+andw_3 ... ok
+andw_4 ... ok
+andw_5 ... ok
+andw_6 ... ok
+andw_7 ... ok
+andl_1 ... ok
+andl_2 ... ok
+andl_3 ... ok
+andl_4 ... ok
+andl_5 ... ok
+andl_6 ... ok
+andl_7 ... ok
+andq_1 ... ok
+andq_2 ... ok
+andq_3 ... ok
+andq_4 ... ok
+andq_5 ... ok
+andq_6 ... ok
+andq_7 ... ok
+andq_8 ... ok
+andq_9 ... ok
+andq_10 ... ok
+bsfw_1 ... ok
+bsfw_2 ... ok
+bsfl_1 ... ok
+bsfl_2 ... ok
+bsfq_1 ... ok
+bsfq_2 ... ok
+bsrw_1 ... ok
+bsrw_2 ... ok
+bsrl_1 ... ok
+bsrl_2 ... ok
+bsrq_1 ... ok
+bsrq_2 ... ok
+bswapl_1 ... ok
+bswapq_1 ... ok
+btw_1 ... ok
+btw_2 ... ok
+btw_3 ... ok
+btw_4 ... ok
+btl_1 ... ok
+btl_2 ... ok
+btl_3 ... ok
+btl_4 ... ok
+btl_5 ... ok
+btl_6 ... ok
+btl_7 ... ok
+btl_8 ... ok
+btq_1 ... ok
+btq_2 ... ok
+btq_3 ... ok
+btq_4 ... ok
+btq_5 ... ok
+btq_6 ... ok
+btq_7 ... ok
+btq_8 ... ok
+btcw_1 ... ok
+btcw_2 ... ok
+btcw_3 ... ok
+btcw_4 ... ok
+btcl_1 ... ok
+btcl_2 ... ok
+btcl_3 ... ok
+btcl_4 ... ok
+btcl_5 ... ok
+btcl_6 ... ok
+btcl_7 ... ok
+btcl_8 ... ok
+btcq_1 ... ok
+btcq_2 ... ok
+btcq_3 ... ok
+btcq_4 ... ok
+btcq_5 ... ok
+btcq_6 ... ok
+btcq_7 ... ok
+btcq_8 ... ok
+btrw_1 ... ok
+btrw_2 ... ok
+btrw_3 ... ok
+btrw_4 ... ok
+btrl_1 ... ok
+btrl_2 ... ok
+btrl_3 ... ok
+btrl_4 ... ok
+btrl_5 ... ok
+btrl_6 ... ok
+btrl_7 ... ok
+btrl_8 ... ok
+btrq_1 ... ok
+btrq_2 ... ok
+btrq_3 ... ok
+btrq_4 ... ok
+btrq_5 ... ok
+btrq_6 ... ok
+btrq_7 ... ok
+btrq_8 ... ok
+btsw_1 ... ok
+btsw_2 ... ok
+btsw_3 ... ok
+btsw_4 ... ok
+btsl_1 ... ok
+btsl_2 ... ok
+btsl_3 ... ok
+btsl_4 ... ok
+btsl_5 ... ok
+btsl_6 ... ok
+btsl_7 ... ok
+btsl_8 ... ok
+btsq_1 ... ok
+btsq_2 ... ok
+btsq_3 ... ok
+btsq_4 ... ok
+btsq_5 ... ok
+btsq_6 ... ok
+btsq_7 ... ok
+btsq_8 ... ok
+cbw_1 ... ok
+cbw_2 ... ok
+cdq_1 ... ok
+cdq_2 ... ok
+cdqe_1 ... ok
+cdqe_2 ... ok
+cld_1 ... ok
+cld_2 ... ok
+cmpb_1 ... ok
+cmpb_2 ... ok
+cmpb_3 ... ok
+cmpb_4 ... ok
+cmpb_5 ... ok
+cmpb_6 ... ok
+cmpb_7 ... ok
+cmpb_8 ... ok
+cmpb_9 ... ok
+cmpb_10 ... ok
+cmpb_11 ... ok
+cmpb_12 ... ok
+cmpb_13 ... ok
+cmpb_14 ... ok
+cmpb_15 ... ok
+cmpb_16 ... ok
+cmpb_17 ... ok
+cmpb_18 ... ok
+cmpb_19 ... ok
+cmpb_20 ... ok
+cmpb_21 ... ok
+cmpb_22 ... ok
+cmpb_23 ... ok
+cmpb_24 ... ok
+cmpb_25 ... ok
+cmpb_26 ... ok
+cmpb_27 ... ok
+cmpb_28 ... ok
+cmpb_29 ... ok
+cmpb_30 ... ok
+cmpb_31 ... ok
+cmpb_32 ... ok
+cmpb_33 ... ok
+cmpb_34 ... ok
+cmpb_35 ... ok
+cmpb_36 ... ok
+cmpb_37 ... ok
+cmpb_38 ... ok
+cmpb_39 ... ok
+cmpb_40 ... ok
+cmpb_41 ... ok
+cmpb_42 ... ok
+cmpb_43 ... ok
+cmpb_44 ... ok
+cmpb_45 ... ok
+cmpb_46 ... ok
+cmpb_47 ... ok
+cmpb_48 ... ok
+cmpb_49 ... ok
+cmpb_50 ... ok
+cmpb_51 ... ok
+cmpb_52 ... ok
+cmpb_53 ... ok
+cmpb_54 ... ok
+cmpb_55 ... ok
+cmpb_56 ... ok
+cmpb_57 ... ok
+cmpb_58 ... ok
+cmpb_59 ... ok
+cmpb_60 ... ok
+cmpw_1 ... ok
+cmpw_2 ... ok
+cmpw_3 ... ok
+cmpw_4 ... ok
+cmpw_5 ... ok
+cmpw_6 ... ok
+cmpw_7 ... ok
+cmpw_8 ... ok
+cmpw_9 ... ok
+cmpw_10 ... ok
+cmpw_11 ... ok
+cmpw_12 ... ok
+cmpw_13 ... ok
+cmpw_14 ... ok
+cmpw_15 ... ok
+cmpw_16 ... ok
+cmpw_17 ... ok
+cmpw_18 ... ok
+cmpw_19 ... ok
+cmpw_20 ... ok
+cmpw_21 ... ok
+cmpw_22 ... ok
+cmpw_23 ... ok
+cmpw_24 ... ok
+cmpw_25 ... ok
+cmpw_26 ... ok
+cmpw_27 ... ok
+cmpw_28 ... ok
+cmpw_29 ... ok
+cmpw_30 ... ok
+cmpw_31 ... ok
+cmpw_32 ... ok
+cmpw_33 ... ok
+cmpw_34 ... ok
+cmpw_35 ... ok
+cmpw_36 ... ok
+cmpw_37 ... ok
+cmpw_38 ... ok
+cmpw_39 ... ok
+cmpw_40 ... ok
+cmpw_41 ... ok
+cmpw_42 ... ok
+cmpw_43 ... ok
+cmpw_44 ... ok
+cmpw_45 ... ok
+cmpw_46 ... ok
+cmpw_47 ... ok
+cmpw_48 ... ok
+cmpw_49 ... ok
+cmpw_50 ... ok
+cmpw_51 ... ok
+cmpw_52 ... ok
+cmpw_53 ... ok
+cmpw_54 ... ok
+cmpw_55 ... ok
+cmpw_56 ... ok
+cmpw_57 ... ok
+cmpw_58 ... ok
+cmpw_59 ... ok
+cmpw_60 ... ok
+cmpw_61 ... ok
+cmpw_62 ... ok
+cmpw_63 ... ok
+cmpw_64 ... ok
+cmpw_65 ... ok
+cmpw_66 ... ok
+cmpw_67 ... ok
+cmpw_68 ... ok
+cmpw_69 ... ok
+cmpw_70 ... ok
+cmpw_71 ... ok
+cmpw_72 ... ok
+cmpw_73 ... ok
+cmpw_74 ... ok
+cmpw_75 ... ok
+cmpw_76 ... ok
+cmpw_77 ... ok
+cmpw_78 ... ok
+cmpw_79 ... ok
+cmpw_80 ... ok
+cmpl_1 ... ok
+cmpl_2 ... ok
+cmpl_3 ... ok
+cmpl_4 ... ok
+cmpl_5 ... ok
+cmpl_6 ... ok
+cmpl_7 ... ok
+cmpl_8 ... ok
+cmpl_9 ... ok
+cmpl_10 ... ok
+cmpl_11 ... ok
+cmpl_12 ... ok
+cmpl_13 ... ok
+cmpl_14 ... ok
+cmpl_15 ... ok
+cmpl_16 ... ok
+cmpl_17 ... ok
+cmpl_18 ... ok
+cmpl_19 ... ok
+cmpl_20 ... ok
+cmpl_21 ... ok
+cmpl_22 ... ok
+cmpl_23 ... ok
+cmpl_24 ... ok
+cmpl_25 ... ok
+cmpl_26 ... ok
+cmpl_27 ... ok
+cmpl_28 ... ok
+cmpl_29 ... ok
+cmpl_30 ... ok
+cmpl_31 ... ok
+cmpl_32 ... ok
+cmpl_33 ... ok
+cmpl_34 ... ok
+cmpl_35 ... ok
+cmpl_36 ... ok
+cmpl_37 ... ok
+cmpl_38 ... ok
+cmpl_39 ... ok
+cmpl_40 ... ok
+cmpl_41 ... ok
+cmpl_42 ... ok
+cmpl_43 ... ok
+cmpl_44 ... ok
+cmpl_45 ... ok
+cmpl_46 ... ok
+cmpl_47 ... ok
+cmpl_48 ... ok
+cmpl_49 ... ok
+cmpl_50 ... ok
+cmpl_51 ... ok
+cmpl_52 ... ok
+cmpl_53 ... ok
+cmpl_54 ... ok
+cmpl_55 ... ok
+cmpl_56 ... ok
+cmpl_57 ... ok
+cmpl_58 ... ok
+cmpl_59 ... ok
+cmpl_60 ... ok
+cmpl_61 ... ok
+cmpl_62 ... ok
+cmpl_63 ... ok
+cmpl_64 ... ok
+cmpl_65 ... ok
+cmpl_66 ... ok
+cmpl_67 ... ok
+cmpl_68 ... ok
+cmpl_69 ... ok
+cmpl_70 ... ok
+cmpl_71 ... ok
+cmpl_72 ... ok
+cmpl_73 ... ok
+cmpl_74 ... ok
+cmpl_75 ... ok
+cmpl_76 ... ok
+cmpl_77 ... ok
+cmpl_78 ... ok
+cmpq_1 ... ok
+cmpq_2 ... ok
+cmpq_3 ... ok
+cmpq_4 ... ok
+cmpq_5 ... ok
+cmpq_6 ... ok
+cmpq_7 ... ok
+cmpq_8 ... ok
+cmpq_9 ... ok
+cmpq_10 ... ok
+cmpq_11 ... ok
+cmpq_12 ... ok