Implemented ARM/AArch64/MIPS switch detection

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#6 · Created  · Last updated

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Merged in AlexAltea/nucleus (pull request #6)

8c4be30·Author: ·Closed by: ·2017-10-02

Description

This patch implements the switch detection passes for ARM/AArch64/MIPS and fixes a couple of issues with the ARM/MIPS disassembler (e.g. mislabeled instructions, delay slot issues).

Pending:

  • Support for little-endian MIPS/PPC: Shouldn't be to hard, just detecting the endianness from the ELF's identification header and switch between read_be and read_le accordingly.

  • Support for MIPS64* (PIC): The instruction sequences to load the jump table base address involve some memory accesses.

  • Fixing issues with the MIPS delay slot: Although I modifies the disassembler to support it, manual testing reveals some issues (padding nop's being detected as reachable for some weird reason). I need to debug it.

PS: I've extended the scripts and configuration files from the virtual machine from the “An In-Depth Analysis of Disassembly on Full-Scale x86/x64 Binaries” paper to compile the SPEC CPU2006 benchmarks for: arm, aarch64, mips, mipsel, mips64, mips64el, powerpc, powerpc64, powerpc64le, and computing the F-scores as done in the Nucleus paper. I'll provide the detailed results ASAP.

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