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README

This is the Verilog HDL implementation of RECTANGLE 80 &128 bit versions

Project Achitecture

. |-- README.md |-- RECTANGLE_128_roundbased | |-- rtl | | |-- mainfsm.v | | |-- p_shift_key.v | | |-- p_shift_state.v | | |-- rcxor.v | | |-- rectangle.v | | |-- reg_key.v | | |-- reg_state.v | | |-- sboxbank.v | | |-- sbox.v | | -- xor64.v |-- tb | -- tb_rectangle.v-- RECTANGLE_80_roundbased |-- rtl | |-- mainfsm.v | |-- p_shift_key.v | |-- p_shift_state.v | |-- rcxor.v | |-- rectangle.v | |-- reg_key.v | |-- reg_state.v | |-- sboxbank.v | |-- sbox.v | -- xor64.v-- tb `-- tb_rectangle.v

Who do I talk to?

http://homes.esat.kuleuven.be/~byang/