System Bus

This bus system is needed to control the components on the adapter, to save pins of the FPGA and simultaneously increase the maximum number of different periphery devices, needed to make a sophisticated FPGA adapter.
All pins that are not used for the TI-99/4A System Interface and not used for the system bus, called GPIO pins, can be used for board internals.

Definition

This adapter internal bus system consists of some Port Selectors that selects which part of the TI System Interface is active (the console, the CPU, both or non of it) and an Device Address Bus (DAB[0..2]), which is available as separate Device Selectors. From these 3 address bits you can address a maximum of 8 devices, each with an 16 bit wide Device Data Bus (DDB[0..15]). Because the TMS9900 CPU has a 16 bit data bus, the system Device Data Bus should also be 16 bit wide.
This Device Data Bus is not a direct part of the System Bus, it is mapped with the the first 16 GPIO signals and is only used as a data bus when one of the Device Selectors are active.
Like the Device Data Bus the Memory Address Bus (MAB[0..20]) is also not a direct part of the System Bus. It is a device specific bus (only used for accessing the SRAM) and mapped with the next 20 GPIO signals (starting with GPIO16).
For decoding the Device Selectors (and to reduce pin usage of the FPGA), an dedicated decoder circuit on board is necessary. An 3:8 decoder (74LCX138) is used on board instead of using 8 dedicated separate FPGA pins.

System Bus Overview

This list contains all relevant names of signals of the System Bus. Here you can also see all different pin configurations. The name of the device specific signals came from the pin descriptions of each module. The characters surrounded by braces indicates the direction of the specified GPIO pin: I = Input; O = Output
If nothing is specified the direction is bidirectional (I/O).

^* The VGA signals are always active! So when using the VGA module, GPIO[37..47] always configured as output and used to generate the video signal. This signals cannot be used in other ways.

Device Selector Assignment

Device Selector ID assignment:

FPGA Adapter

This device (ID 0) is reserved for FPGA internal use, indicating that device dependent buses are not used. All of the GPIO lines can be used as you like.

SRAM

The SRAM device (ID 1, 2) is a bit exceptional from the general form of an device: To be able to address a large amount of memory, an extra address bus is needed, the Memory Address Bus (MAB) exists in parallel to the Device Address Bus. The address bits DAB[0..2] are just for selecting devices, but MAB[0..20] is used for addressing the memory area.
While one of the both SRAM enabling signals are active, the whole GPIO bus is not available and cannot be used otherwise! GPIO[16..36] are then used as the Memory Address Bus defined as MAB[0..20]. The bits GPIO[37..47] are reserved for future use (i.e. for massive memory expansion or what else).
The decision to use static RAM is made because data retaining (through a simple battery) is necessary for using this RAM/GROM or RAM Disk. Due to a very complicated protocol that synchronous DRAM uses, I won't waste FPGA logic for that.

LCD Device

The LCD device port (ID 3) uses DDB[0..7] for data exchange. GPIO 16 is used for selecting Instruction Registers (low, write only) or Data Register (high, read/write).

Key Pads

This device (ID 4) addresses two different key pads: The 4x4 and the 8 push button key pads. Both key pads are using the 16 bit data bus.
The 4x4 keys must address one of 4 rows through DDB[0..3], the pressed keys for that row are delivered through the column lines (DDB[4..7]).
Each of the 8 push buttons are represented through DDB[8..15] and are active heigh.

SPI

This device (ID 5) stands for a special group of serial attached devices: F-RAM/Data Flash, memory devices which retains their content or an external PS/2 connected Keyboard/Mouse.
Currently there are three serial devices which are sharing the bits DDB[0..10]. The PS2 connection is only used when the VGA circuit module is applied.

The F-RAM device is a 2k Byte ferroelectric nonvolatile RAM, used for storing configurations like lists of breakpoints, has a two wire protocol. To access it, use DDB[0..10] as follows:

• DDB0 used as SDA (serial data/address)
• DDB1 - SCL (serial clock)
• DDB2 not used
• DDB[3..8] reserved for DataFlash device
• DDB[9..10] reserved for a PS2 device

The DataFlash device is a 512k Byte Flash memory and is used to store software used by the TI permanently (like a DSR for this FPGA adapter). The stored programs will be loaded into a SRAM area at startup time. The device has a serial peripheral interface (SPI). To access this, use DDB[0..10] as follows:

• DDB[0..2] reserved for F-RAM device
• DDB3 used as SO (serial out)
• DDB4 - SI (serial in)
• DDB5 - SCK (serial clock)
• DDB6 - WP (write protection)
• DDB7 - RST (reset)
• DDB8 not used
• DDB[9..10] reserved for a PS2 device

The Mouse/Keyboard are PC-Standrad components, connected via PS-2. To access it, use DDB[0..10] as follows:

• DDB[0..2] reserved for F-RAM device
• DDB[3..8] reserved for DataFlash device
• DDB9 used as PS_DATA (serial data)
• DDB10 - PS_CLK (serial clock)

This ID can be used to attach more devices, like CF- or SD-Card reader.

USB Device

Another (and additionally) way for configuring and controlling the debugger (or other FPGA implementations) is to connect another (modern) computer via an USB interface. A special binary protocol will handle all configurations and control.
This device (ID 6) will be configured as an slave, so when connected to an host, the TI will look like an external device.

XBoard

The Expansion Board (XBoard, ID 7) is used for expansion and future use. This board is planned as a daughter board sitting on top of the TI's main board, connected to the Core Modul Adapter (which is also sitting on top of the main board). This Expansion Board will connect the VDP (so you can acces the VDP and its VRAM) and also the Keyboard through available sockets and pin header.
To select the devices owned by the TI-99/4A, this device selector will be used to scale further selectors, named TI Device Selector, by using TDS[0..2].

TI Device Selector ID assignment:

GPIO

Generally all GPIO lines are for free use, but with the exception above for the reserved GPIO while accessing the SRAM or other devices. But to be sure, it is save to use the GPIO signals only while working internally and the FPGA Select signal is activated (active low).