Welcome to PSHDL, a Plain Simple Hardware Description Language. In this document I would like to outline what PSHDL is and what it is aimed to accomplish. Please note that PSHDL is research in progress and the current implementation is far from being finished (thus the Alpha in the logo).

##Downloads If you want to get PSHDL running on your computer, check the Tools page.

##Motivation VHDL is among Verilog a very popular hardware description language that is used to program FPGAs. Common to both is that they can do much more than that. They were originally designed to describe the inner workings of chips. Later some tools where invented to directly generate RTL netlist out of them.

As they were never really designed to program FPGAs, they carry a lot of functional overhead. Also the verbosity of VHDL is quite outdated. In both languages it is very easy to describe something that is not synthesable, or even worse something that works in the simulation but not the actual hardware. It is also very easy to describe latches, while describing registers, the most important part of every synchronous design, takes a lot of discipline to adhere to certain templates. This makes it very frustrating for beginners to properly describe something in VHDL that works in simulation AND synthesis.

##Philosophy

PSHDL is aimed to be a language that makes it easy to write something that can be synthesized and behaves the same in simulation. It reverses the effort to create a latch, you explicitly have to tell the compiler that you want a latch. Creating registers on the other hand is very simple, just tell the compiler that a variable is a register. Of course the expression syntax is much compacter than VHDL and is inspired by C/Java to make it easier for SW developers coming from either language. Another important factor to make the language more usable is to produce meaningful error messages and create a developer friendly IDE. This does not mean that the language can only be used for small academic projects. Its powerful code generation infrastructure allows to create complex designs if necessary.

It also aims to be a very practical language with near-zero academic overhead. I hope that helps to make it more popular :)

Goals

To summarize, these are the goals that PSHDL is aiming to accomplish:

Make it easy to:

• Learn the syntax
• Use registers
• Instantiate other modules/entities
• Describe state machines
• Create synthesizable code
• Extend the language

Make it hard to:

• Create latches
• Create a mismatch between HW and simulation
• To unintentionally lose precision
• Create code that does not synthesize

Further information

If you want to learn more about PSHDL checkout this page about or start with the tutorial.